Semiconductor device and method for manufacturing the same

ABSTRACT

A method for manufacturing a semiconductor device includes forming a device isolation film defining an active region, forming a recess configured to expose a seam contained in the device isolation film by etching the active region and the device isolation film, forming a sacrificial film to fill the exposed seam, and forming a gate at a lower part of the recess.

CROSS-REFERENCE TO RELATED APPLICATION

The priority of Korean patent application No. 10-2013-0057880 filed on22 May 2013, the disclosure of which is hereby incorporated by referencein its entirety, is claimed.

BACKGROUND

Embodiments relate to a semiconductor device and a method formanufacturing the same, and more particularly to a semiconductor devicein which a seam formed in a device isolation film defining an activeregion is filled with a sacrificial film, and a method for manufacturingthe same.

With an increasing integration degree of a semiconductor device, apattern, including a device isolation region, formed over a cell regionof a semiconductor substrate has been reduced to prevent the occurrenceof electric connection between patterns.

A conventional device isolation region has been formed through a localoxidation of silicon (LOCOS) process. As the device isolation region hasbeen gradually reduced in size, a shallow trench isolation (STI) processcapable of forming a superior small-sized device isolation region hasbeen developed as an alternative to the LOCOS process.

In accordance with the STI process, after a trench having apredetermined depth is formed in a semiconductor substrate, aninsulation material is deposited to fill the trench, and an unnecessaryinsulation film is removed through a subsequent CMP process, such that adevice isolation region for electrically isolating active regions isformed.

However, as a design rule is gradually reduced, an aspect ratio of atrench is gradually increased, such that a method for forming a deviceisolation film using the STI process is confronted with the limitationin trench filling.

For example, a void or seam may occur in an insulation film when theinsulation film is filled in the trench, such that reliability andproductivity of a highly-integrated semiconductor device are reduced. Ifthe seam occurs in a device isolation film, a word-line material mayextend into the seam when the word line (gate) is formed in a subsequentprocess, resulting in a bridge between several word lines.

Moreover, when the device isolation film is formed of an oxide film soas to minimize the loss of a silicon substrate as well as to maximize athickness of a wall oxide film, seams (or voids) may occur in the deviceisolation film.

SUMMARY

Various embodiments are directed to providing a semiconductor device anda method for manufacturing the same to address issues of the relatedart.

An embodiment relates to a method for forming a device isolation film ofthe semiconductor device so as to prevent device characteristics frombeing deteriorated by a void and seam created when a trench of a deviceisolation region is filled in the STI process.

In accordance with an aspect of the embodiment, a method formanufacturing a semiconductor device includes: forming a deviceisolation film defining an active region; forming a recess configured toexpose a seam contained in the device isolation film by etching theactive region and the device isolation film; forming a sacrificial filmto fill the exposed seam; and forming a gate in a lower part of therecess.

In accordance with another aspect of the embodiment, a semiconductordevice includes: a device isolation film to define an active region; agate recess exposing the active region and the device isolation film todefine a gate region; and a gate formed in the gate recess, wherein thedevice isolation film includes a first insulation film and a sacrificialfilm filling a seam in the first insulation film.

It is to be understood that both the foregoing general description andthe following detailed description of embodiments are exemplary andexplanatory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a layout of a semiconductor deviceaccording to an embodiment.

FIG. 2 is a cross-sectional view illustrating the semiconductor devicetaken along the lines A-A′, B-B′, and C-C′ of FIG. 1.

FIGS. 3 to 7 are cross-sectional views illustrating a method for formingthe semiconductor device shown in FIG. 2.

FIG. 8 illustrates a sacrificial film of FIG. 6 which is introduced intoboth sides of a seam.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to certain embodiments, exampleswhich are illustrated in the accompanying drawings. Wherever possible,the same reference numbers will be used throughout the drawings to referto the same or like parts. In the following description, a detaileddescription of well-known configurations or functions may be omitted.

FIG. 1 is a plan view illustrating a layout of a semiconductor deviceaccording to an embodiment. FIG. 2 is a cross-sectional viewillustrating the semiconductor device taken along the lines A-A′, B-B′,and C-C′ of FIG. 1.

The semiconductor device according to the embodiment may be configuredto have a 6F² structure in which an active region 104 defined by adevice isolation film 102 is not perpendicular to a gate (word line) 106and is tilted at a predetermined angle other than a right angle withrespect to the gate (word line) 106. In this case, the gate 106 may havea buried gate structure buried below the active region 104. The deviceisolation film 102 and the active region 104 of the gate region may beformed in a fin structure in such a manner that the active region 104 ismore protruded than the device isolation film 102 when viewed from thecross-section B-B′. That is, the buried gate 106 may be in contact witha top surface and sidewalls of the protruded portion of the activeregion 103, such that the buried gate 106 may be formed in a fin gatestructure and channels are formed over the three-dimensional activeregion 103.

The device isolation film 102 according to the embodiment may include asacrificial film 108. In this case, the sacrificial film 108 is formedin a portion where a conventional seam (or void) may arise (referred toas ‘conventional seam formation region’). That is, according to thisembodiment, the sacrificial film 108 is filled in the conventional seamformation region, such that the seam formed in the device isolation film102 is removed (or eliminated).

In accordance with a method for filling the seam with the sacrificialfilm 108, a recess (not shown) for forming the buried gate 106 is formedand an insulation material is buried (gapfilled) in the recess. Since itis difficult to completely gapfill the insulation film for deviceisolation during the formation of the device isolation film 102, thedevice isolation film 102 is formed while having seams (or voids)inside. Thereafter, when the active region 104 and the device isolationfilm 102 are etched to form a recess for a buried gate, the seam isexposed. The exposed seam is gapfilled with an insulation film 108, suchthat the sacrificial film 108 is formed in the device isolation film102. A method for forming the sacrificial film 108 will hereinafter bedescribed in detail. The sacrificial film 108 may be a silicon layer.

Since voids (or seams) which may be created in the trench for deviceisolation can be filled and removed by a sacrificial film formed in thesubsequent process, the trench for device isolation can be formed asdeep as possible without a concern about the voids (or seams). Thus, anelectric field barrier can be formed at such a level as to preventretention time deterioration.

In addition, the trench for device isolation may be filled with theoxide film, preferably, only a high temperature oxide (HTO) film. Whenthe device isolation trench is gap-filled with the oxide film, the oxidefilm may be formed through deposition to a maximum thickness allowed bya given reduced design rule. When the device isolation trench is formedthrough deposition, a width of the protruding portion (channel region ora fin gate region) can be maintained intact. In other words, the activeregion under the buried gate 106 protrudes higher than the deviceisolation region under the buried gate 106. See FIG. 2, B-Bcross-sectional view.

Accordingly, a loss of a silicon layer (active region) forming thechannel region is minimized and a fin gate region can be maintained witha relatively larger width in a subsequent process. Thus, the width ofthe active region under the buried gate 106 (or fin gate region or thechannel region) can be maintained substantially as same as a width ofthe protruded portion of the active region shown in the cross-sectionB-B′ of FIG. 2.

A sealing insulation film 110 for insulating the buried gate 106 isformed over the buried gate 106. The sealing insulation film may includea nitride film. The sealing insulation film 110 is not shown in FIG. 1for convenience of description.

FIGS. 3 to 7 are cross-sectional views illustrating a method for formingthe semiconductor device shown in FIG. 2.

Referring to FIG. 3, a pad oxide film (not shown) and a pad nitride film(not shown) are formed over a semiconductor substrate 300, and aphotoresist film (not shown) is formed over the pad nitride film. Inthis case, the pad oxide film is formed to prevent stress caused by thepad nitride film from being applied to the semiconductor substrate 300.Subsequently, an exposure and development process is performed on thephotoresist film, such that a photoresist pattern (not shown) is formedto define an active region 302.

The pad nitride film and the pad oxide film are etched using thephotoresist pattern as a mask, resulting in formation of a mask pattern.The semiconductor substrate 300 is etched using the hard mask pattern asa mask, such that a device isolation trench 304 is formed to define theactive region 302.

Referring to FIG. 4, the device isolation trench 304 is filled with adevice isolation insulation material, resulting in formation of thedevice isolation film 306. In this case, the device isolation insulationfilm may include an oxide film, and the oxide film may include a HTOfilm having superior step coverage. That is, the oxide film (HTO film)is deposited over an exposed surface of the device isolation trench 304in such a manner that the device isolation trench 304 is filled with theHOT oxide film.

Specifically, when the device isolation film 306 is formed, theformation process of the HTO film and the dry oxidation process arealternately performed. For example, after the HTO film is formed overthe exposed surface of the device isolation trench 304, the dryoxidation process is performed on the HTO film, and the HTO film isfurther formed over the dry oxidation resultant film, as denoted by(HTO+Dry+HTO). If necessary, each of the HTO oxidation process and thedry oxidation process may be performed once. After the formation of theHTO film, an annealing process may be performed on the HTO film suchthat a quality of the oxide film can be enhanced.

After the formation of the device isolation film 306, the pad nitridefilm and the pad oxide film are removed. For example, the pad nitridefilm is removed by a dry etching process using a phosphoric solution,and the pad oxide film is then removed by a wet etching process using ahydrogen fluoride solution.

As described above, when the device isolation film is formed of theoxide film, the same effect is obtained as in the case in which the walloxide film) of a thick thickness is formed, resulting in improvement ofdevice characteristics. However, if the device isolation film is formedof the oxide film only, specifically, if the device isolation film isformed of the HTO film only, a seam 308 occurs in the device isolationfilm. A method for removing the seam 308 according to the embodimentwill hereinafter be described.

Referring to FIG. 5, a mask pattern (not shown) defining the buried gateregion is formed over the active region 302 and the device isolationfilm 306 including the seam. Here, the buried gate region may correspondto a specific region in which the buried gate 106 of FIG. 1 is formed.

Subsequently, the active region 302 and the device isolation film 306are etched using the mask pattern as an etch mask, such that a recess310 for a gate is formed such that the buried gate can be formed in therecess 310. In this case, the device isolation film 306 is more deeplyetched than the active region 302 according to an etch selection ratiobetween the active region 302 and the device isolation film 306,resulting in formation of a fin structure. That is, a bottom of theactive region 302 exposed in the gate recess 310 is more protruded thana bottom of the device isolation film 306 exposed in the gate recess310.

As a result, seams 308 formed in the device isolation film 306 areexposed by the gate recess 310 according to the embodiment. That is,because of the gate recess 310, the seams 308 are exposed at the bottomand sidewalls of the gate recess 310.

Referring to FIG. 6, a sacrificial film 312 is formed over the innersurface of the gate recess 310 in such a manner that the exposed seam308 can be filled with the sacrificial film 312. When forming thesacrificial film 312, most of the seam 308 (See the B-B′ cross-sectionalview and the C-C′ cross-sectional view of FIG. 5) exposed at the bottomof the gate recess 310 have low aspect ratios and thus the sacrificialfilm 312 can be easily filled into the seam 308. In addition, althoughthe seams 308 (See the A-A′ cross-sectional view of FIG. 5) exposed atthe sidewalls of the gate recess 310 tend to have high aspect ratios,the sacrificial film 312 can fill the seams 308 by being introduced fromsides of the seam 308 to the inside of the seams 308 through the gaterecess 310 as shown in arrows of FIG. 8, instead of being introducedfrom an upper portion of the seams 308. Accordingly, the sacrificialfilm 312 can be easily introduced into the inside of the seam 308 whichare exposed at the sidewalls of the gate recess 310. In FIG. 8, only oneseam among several seams formed in the device isolation film 306 betweenthe gate recesses 310 is denoted by a dotted line for convenience ofdescription. In addition, each arrow marked at both sides of the seam308 of FIG. 8 indicates the direction along which the sacrificial film312 is introduced into the seam 308. The sacrificial film 312 may bereplaced with silicon (Si). When the sacrificial film 312 includessilicon (Si), the silicon (Si) will be oxidized in a subsequent process.Alternatively, the sacrificial film 312 may include a nitride film. Forexample, Atomic Layer Deposition (ALD) or Chemical Vapor Deposition(CVD) may be used to fill the seam 308 with the sacrificial film 312.

If the seam 308 is buried (gapfilled) with the sacrificial film 312, thesacrificial film 312 formed over the active region 302 and the deviceisolation film 306 is oxidized, such that a gate insulation film 314 forcapping the sacrificial film 312 is formed over the inner surface of thegate recess 310. Alternatively, after the sacrificial film 312 remainingover the active region 302 and the device isolation film 306 is removed,the gate insulation film 314 may be formed over the active region 302and the device isolation film 306 exposed in the gate recess 310, suchthat the sacrificial film 312 is covered with the gate insulation film314. The gate insulation film 314 may be formed by oxidizing thesacrificial film 312 located in the active region 302 and the deviceisolation film 306 through radical oxidation. In another example, a highdielectric material having a high permittivity is deposited over theactive region 302 and the device isolation film 306 in the gate recess310 using Atomic Layer Deposition (ALD) or Chemical Vapor Deposition(CVD), such that the gate insulation film 314 can be formed.

Referring to FIG. 7, after the gate recess 310 is filled with aconductive film for the gate, the gate conductive film is planarized orsubject to a CMP process. In this case, the gate conductive film may bea single metal material such as titanium (Ti), titanium nitride (TiN),tungsten (W) or tungsten nitride (WN), or a combination thereof.Alternatively, other conductive material such as a doped polysiliconmaterial may be used as the gate conductive film.

Thereafter, the gate conductive film is selectively removed in such amanner that the gate conductive film of a predetermined thicknessremains at a lower part of the gate recess 310, resulting in formationof a buried gate 316. In this case, an upper part of the gate conductivefilm may be selectively removed through an etch-back process.

Subsequently, a sealing insulation film 318 is formed over the buriedgate 316 in such a manner that the gate recess 310 is filled with thesealing insulation film 318. The sealing insulation film 318 may includea silicon nitride (Si₃N₄) film. Chemical vapor deposition (CVD) may beused as a method for forming the sealing insulation film 318. In thiscase, the CVD may include Atmospheric Pressure CVD (APCVD), Low PressureCVD (LPCVD), Plasma Enhanced CVD (PECVD), Metal Organic CVD (MOCVD), andthermal CVD.

The subsequent fabrication processes may be performed in a similarmanner as those for a semiconductor device including a typical buriedgate structure, and as such a detailed description thereof will hereinbe omitted for convenience of description.

As is apparent from the above description, since the device isolationfilm is formed of an oxide material and a thicker wall oxide film isguaranteed, various operation characteristics of the semiconductordevice can be enhanced. For example, reliability of a data retentiontime (tREF) increases, a word-line dist (WL-Dist) characteristic isimproved, channel resistance is reduced, and a hot electron inducedpunch-through (HEIP) phenomenon is prevented from occurring in atransistor of the peripheral region.

In accordance with the embodiments, when the device isolation film isformed of an oxide film, a seam possibly existing in the deviceisolation film can be easily removed, and gapfill characteristics of thedevice isolation film can be improved.

In addition, the number of fabrication processes of the semiconductordevice can be simplified or reduced when the device isolation film isformed by the above fabrication method shown in the embodiments.

Those skilled in the art will appreciate that the present embodimentsmay be carried out in other ways other than those set forth hereinwithout departing from the spirit and essential characteristics of thepresent embodiments. The above exemplary embodiments are therefore to beconstrued in all aspects as illustrative and not restrictive.

The above embodiments are illustrative and not limitative. Variousalternatives are possible. The embodiments are not limited by the typeof deposition, etching polishing, and patterning steps described herein.Nor are the embodiments limited to any specific type of semiconductordevice. For example, the present embodiments may be implemented indynamic random access memory (DRAM) devices or non-volatile memorydevices. Other additions, subtractions, or modifications can be made.

1.-12. (canceled)
 13. A semiconductor device comprising: a deviceisolation film to define an active region; a gate recess exposing theactive region and the device isolation film to define a gate region; anda gate formed in the gate recess, wherein the device isolation filmincludes a first insulation film and a sacrificial film filling a seamin the first insulation film.
 14. The semiconductor device according toclaim 13, wherein the sacrificial film includes a nitride film orsilicon.
 15. The semiconductor device according to claim 13, wherein thefirst insulation film includes a high temperature oxide (HTO) film. 16.The semiconductor device according to claim 13, wherein the gate recessincludes a fin structure in which the active region under the gate isprotruded higher than the device isolation film under the gate.